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PM6344 Datasheet(PDF) 88 Page - PMC-Sierra, Inc

Part # PM6344
Description  QUADRUPLE E1 FRAMER
PDF  256 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 88 Page - PMC-Sierra, Inc

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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
75
Input Transmit Data
Bit Settings
XCLK Freq Effect on Output Transmit
Data
Backplane transmit
data timed to
BTCLK[x].
HSBPSEL
=0
XCLKSEL
=0
OCLKSEL1 =0
OCLKSEL0 =1
PLLREF1
=X
PLLREF0
=X
TCLKISEL
=0
SMCLKO
=0
XCLKSEL
=1
TCLKISEL
=1
SMCLKO
=1
49.152MHz
16.384MHz
No jitter attenuation.
TCLKO[x] is equal to
TCLKI[x] (useful for higher
rate MUX applications).
Same as above.
Backplane transmit
data timed to
BTCLK[x].
HSBPSEL
=0
XCLKSEL
=0
OCLKSEL1 =0
OCLKSEL0 =0
PLLREF1
=X
PLLREF0
=X
TCLKISEL
=0
SMCLKO
=1
XCLKSEL
=1
49.152MHz
16.384MHz
TCLKI[x] is a jitter-free
16.384MHz clock.
TCLKO[x] is equal to
TCLKI[x]÷8.1
Same as above.
Backplane transmit
data timed to
BTCLK[x].
HSBPSEL
=0
XCLKSEL
=1
OCLKSEL1 =0
OCLKSEL0 =0
PLLREF1
=X
PLLREF0
=X
TCLKISEL
=1
SMCLKO
=1
jitter-free
16.384MHz
XCLK is a jitter-free
16.384MHz clock.
TCLKO[x] is equal to
XCLK÷8.1
1. The register bits SYNC, CENT, and LIMIT in the DJAT Configuration Register
must be set to logic 0 in these configurations.
Upon reset of the EQUAD, these bits are cleared to zero, selecting digital jitter
attenuation with TCLKO[x] referenced to the backplane transmit clock, BTCLK[x].
Figure 8 illustrates the various bit setting options, with the reset condition
highlighted.



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