PM6344 datasheet(60/256 Pages) PMC

60 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

updated on either the rising or falling edge of TCLKO[x]. When the interface is

configured for single-rail output, the multifunctional pins become the TDD[x] and

TFLG[x] outputs, which can be enabled to be updated on either the rising or

falling TCLKO[x] edge. Further, the TFLG[x] output can be enabled to indicate

FIFO empty or FIFO full status.

The DTIF block also provides Alarm Indication Signaling (AIS) generation

capability by generating alternating mark signals on the TDP/TDN[x] outputs, or

all-ones on the TDD[x] output, when the TAISEN bit is set in the Transmit E1

Interface Configuration register. This is useful when the internal loopback modes

are used.

8.15 Backplane Transmit Interface (BTIF)

The Backplane Transmit Interface allows data to be taken from a backplane in

either a 2.048 Mbit/s or 16.384 Mbit/s serial stream and allows BPV transparency

by accepting dual-rail data input at 2.048 Mbit/s.

When configured to receive a 2.048 Mbit/s data rate stream, the block expects

the input data stream on the BTPCM[x] pin to contain 32 timeslots. The

BTSIG[x] input pin must contain 30 bytes of signaling nibble data located in the

least significant nibble of each byte. The framing alignment indication on the

BTFP[x] pin indicates the framing bit position of the 256-bit frame (or, optionally,

the framing bit position of the first frame of the signaling multiframe frame, and

the CRC multiframe).

When configured to interface to a 16.384 Mbit/s serial stream, the four sets of

PCM and signaling streams are expected to be bit interleaved. The MTFP pin

marks the framing bit position of the first multiplexed PCM stream (destined for

transmitter number one) or, optionally, the framing bit position of the first frame of

the signaling multiframe frame, and the CRC multiframe. MTFP operates in a

similar fashion to BTFP[x], but is only valid at positions coincident with the first

multiplexed PCM stream. All four multiplexed interfaces will have the same

frame, signaling multiframe, and CRC multiframe alignment. See the Functional

Timing section for more details.

8.16 Microprocessor Interface (MPIF)

The Microprocessor Interface allows the EQUAD to be configured, controlled and

monitored via internal registers.

PM6344 Datasheet(PDF) 60 Page - PMC-Sierra, Inc