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PM6344 Datasheet(PDF) 92 Page - PMC-Sierra, Inc

Part # PM6344
Description  QUADRUPLE E1 FRAMER
PDF  256 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 92 Page - PMC-Sierra, Inc

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STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
79
that is logic 1. Any combination enable bits is allowed resulting in a data rate
between 4 kbit/s and 20 kbit/s.
If all RXSAxEN (where x is the values 4 to 8 inclusive) bits are set to logic 0,
Timeslot 16 is extracted and treated as a data link. If RXDMASIG is set to
logic 0, Timeslot16 is made available on the RDLSIG[x] output and
RDLCLK[x] is an associated 64 kHz clock. If RXDMASIG is logic 1, the data
link is terminated by the HDLC receiver and the RDLINT/RDLSIG[x] and
RDLEOM/RDLCLK[x] pins operate as a data link interrupt (RDLINT[x]) and a
end-of-message (RDLEOM[x]) indication.
Note that the RFRACE1 bit will force fractional E1 channel outputs on
RDLINT/RDLSIG[x] and RDLEOM/RDLCLK[x] if it is set to logic 1 as it has
the highest priority over the control of these outputs.
Upon reset of the EQUAD, all bits are logic 0 except RXSA4EN. By default, a 4
kbit/s data link is extracted from Sa4 and presented on the RDLSIG output.



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