PM6344 datasheet(89/256 Pages) PMC

89 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Figure 8

- Transmit Timing Options

DJAT

FIFO

BTCLK[x]

BTXCLK

FIFO input

data clock

OCLKSEL1

DJAT

PLL

PLLREF[1:0]

RCLKO[x]

TCLKI[x]

SMCLKO

Smooth 2.048MHz

Smooth

16.384

MHz

÷ 8

OCLKSEL0

TCLKISEL

XCLK

XCLKSEL

HSBPSEL

÷ 2

(49.152MHz or

16.384MHz)

"Jitter-free"

2.048MHz

"Jitter-free"

16.384MHz

"High-speed" clock for CDRC

& FRMR (=16.384MHz)

"High-speed" clock for ELST,

SIGX, TPSC & RPSC (•6x max

backplane clockrate)

FIFO output

data clock

TCLKO[x]

÷ 3

24X reference clock

for jitter attenuation

This diagram illustrates clock configurations for when the RCLKOSEL bit is set to

logic 0. See the Operations - Receiver Jitter Attenuation section for DJAT clock

configurations when RCLKOSEL is set to logic 1.

The DJAT requires a 49.152MHz clock; if a 16.384MHz clock is used for XCLK,

then the DJAT will not function and should be bypassed.

PM6344 Datasheet(PDF) 89 Page - PMC-Sierra, Inc

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