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DM505 Datasheet(PDF) 158 Page - Texas Instruments

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Part # DM505
Description  SoC for Radar and Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
PDF  286 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM505 Datasheet(HTML) 158 Page - Texas Instruments

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A0
A1
B0 B1
A30 A31
B30 B31 C0
C1 C2
C3
C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
ACLKR/X (CLKRP = CLKXP = 0)(B)
ACLKR/X (CLKRP = CLKXP = 1)(A)
SPRS91v_McASP_02
158
DM505
SPRS976A – NOVEMBER 2016 – REVISED JANUARY 2017
www.ti.com
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Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
A.
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B.
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 5-44. McASP Output Timing
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented Table 4-28 and described in Device TRM, Control
Module section.



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