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DM505 Datasheet(PDF) 159 Page - Texas Instruments |
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DM505 Datasheet(HTML) 159 Page - Texas Instruments |
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159 / 286 page  159 DM505 www.ti.com SPRS976A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated CAUTION The IO timings provided in this section are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-58. In Table 5-58 are presented the specific groupings of signals (IOSET) for use with McASP1. Table 5-58. McASP1 IOSETs SIGNALS IOSET1 IOSET2 IOSET3 BALL MUX BALL MUX BALL MUX mcasp1_aclkx U17 1 U17 1 U17 1 mcasp1_fsx W17 1 W17 1 W17 1 mcasp1_aclkr AA17 1 mcasp1_fsr U16 1 mcasp1_axr0 W16 1 W16 1 W16 1 mcasp1_axr1 V16 1 V16 1 V16 1 mcasp1_axr2 U15 1 mcasp1_axr3 V15 1 mcasp1_axr4 Y15 1 mcasp1_axr5 W15 1 mcasp1_axr6 AA15 1 mcasp1_axr7 AB15 1 mcasp1_axr8 AA14 1 AA14 1 U15 4 mcasp1_axr9 AB14 1 AB14 1 V15 4 mcasp1_axr10 U13 1 Y15 4 mcasp1_axr11 V13 1 W15 4 mcasp1_axr12 Y13 1 AA15 4 mcasp1_axr13 W13 1 AB15 4 mcasp1_axr14 U11 1 U7 4 mcasp1_axr15 V11 1 V7 4 5.9.6.13 DCAN and MCAN 5.9.6.13.1 DCAN The device provides one DCAN interface for supporting distributed realtime control with a high level of security. The DCAN interface implements the following features: • Supports CAN protocol version 2.0 part A, B • Bit rates up to 1 MBit/s • 64 message objects • Individual identifier mask for each message object • Programmable FIFO mode for message objects • Programmable loop-back modes for self-test operation • Suspend mode for debug support • Automatic bus on after Bus-Off state by a programmable 32-bit timer • Message RAM single error correction and double error detection (SECDED) mechanism • Direct access to Message RAM during test mode • Support for two interrupt lines: Level 0 and Level 1, plus separate ECC interrupt line |
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