LPC18S50 datasheet(59/151 Pages) NXP

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LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

59 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

[1]

N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in

the SFS register to enable the input buffer; I = input; OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA

= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset

without boot code operation.

[2]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength (see Figure 44).

[3]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels, and hysteresis; high drive strength (see Figure 44).

[4]

5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed

digital I/O functions with TTL levels and hysteresis (see Figure 44).

[5]

5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;

if VDDIO not present, do not exceed 3.6 V). When configured as an ADC input or DAC output, the pin is not 5 V tolerant and the digital

section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP

[6]

5 V tolerant transparent analog pad.

[7]

For maximum load CL = 6.5 F and maximum pull-down resistance Rpd = 80 k, the VBUS signal takes about 2 s to fall from VBUS =

5 V to VBUS = 0.2 V when it is no longer driven.

[8]

Transparent analog pad. Not 5 V tolerant.

[9]

Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode

only).

[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to

provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.

[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output and hysteresis (see Figure 45).

[12] If not pinned out, VPP is internally connected to VDDIO.

[13] On the TFBGA100 package, VSS is internally connected to VSSIO.

VSSIO

C4,

D13,

G6,

G7,

G8,

H8,

H9,

J8,

J9,

K9,

K10,

M13,

P7,

P13

40,

76,

109

[13]

Ground.

VSSA

135

Analog ground.

Not connected

-B9

n.c.

Table 3.

Pin description …continued

LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.

Symbol

Description

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