LPC18S50 datasheet(80/151 Pages) NXP

80 / 151 page

LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

80 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

• RTC power supply is isolated from the rest of the chip.

• Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.

• Periodic interrupts can be generated from increments of any field of the time registers.

• Alarm interrupt can be generated for a specific date/time.

7.17.2 Alarm timer

The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating

alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00

and asserts an interrupt if enabled.

The alarm timer is part of the RTC power domain and can be battery powered.

7.18 System control

7.18.1 Configuration registers (CREG)

The following settings are controlled in the configuration register block:

• BOD trip settings

• Oscillator output

• DMA-to-peripheral muxing

• Ethernet mode

• Memory mapping

• Timer/USART inputs

• Enabling the USB controllers

In addition, the CREG block contains the part identification and part configuration

information.

7.18.2 System Control Unit (SCU)

The system control unit determines the function and electrical mode of the digital pins. By

default function 0 is selected for all pins with pull-up enabled. For pins that support a

digital and analog function, the ADC function select registers in the SCU enable the

analog function.

A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are

located on separate pads and are not controlled through the SCU.

In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that

select the pin interrupts are located in the SCU.

7.18.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be

unrelated in frequency and phase and can have different clock sources within the CGU.

One CGU base clock is routed to the CLKOUT pins. The base clock that generates the

CPU clock is referred to as CCLK.

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