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LPC18S50 Datasheet(PDF) 63 Page - NXP Semiconductors |
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LPC18S50 Datasheet(HTML) 63 Page - NXP Semiconductors |
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63 / 151 page  LPC18S50_S30_S10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 1 — 23 February 2015 63 of 151 NXP Semiconductors LPC18S50/S30/S10 32-bit ARM Cortex-M3 microcontroller 7.8.1 ISP (In-System Programming) mode In-System Programming (ISP) means programming or reprogramming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. ISP can be performed when the part resides in the end-user board. ISP loads data into on-chip SRAM and execute code from on-chip SRAM. 7.9 Boot ROM The internal ROM memory is used to store the boot code of the LPC18S50/S30/S10. After a reset, the ARM processor will start its code execution from this memory. The boot ROM memory includes the following features: • The ROM memory size is 64 kB. • Supports booting from external static memory such as NOR flash, SPI flash, quad SPI flash, USB0, and USB1. • Includes API for OTP programming. • Includes a flexible USB device stack that supports Human Interface Device (HID), Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers. Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1. [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Remark: Pin functions for SPIFI and SSP0 boot are different. Table 4. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC bit 3 BOOT_SRC bit 2 BOOT_SRC bit 1 BOOT_SRC bit 0 Description Pin state 0 0 0 0 Boot source is defined by the reset state of P1_1, P1_2, P2_8, and P2_9 pins. See Table 5. USART0 0 0 0 1 Boot from device connected to USART0 using pins P2_0 and P2_1. SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI interface using pins P3_3 to P3_8. EMC 8-bit 0 0 1 1 Boot from external static memory (such as NOR flash) using CS0 and an 8-bit data bus. EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR flash) using CS0 and a 16-bit data bus. EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR flash) using CS0 and a 32-bit data bus. USB0 011 0Boot from USB0. USB1 011 1Boot from USB1. SPI (SSP0) 1 0 0 0 Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7 (function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]. USART3 1 0 0 1 Boot from device connected to USART3 using pins P2_3 and P2_4. |
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