LPC18S50 datasheet(67/151 Pages) NXP

67 / 151 page

LPC18S50_S30_S10

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 23 February 2015

67 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

7.11 One-Time Programmable (OTP) memory

The OTP provides 64 bit One-Time Programmable (OTP) memory for general-purpose

use. 256 bit of OTP memory are available to store two AES keys in two memory banks.

One bank is encrypted.

7.12 General-Purpose I/O (GPIO)

The LPC18S50/S30/S10 provides eight GPIO ports with up to 31 GPIO pins each.

Device pins that are not connected to a specific peripheral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back as well as the current state of the port pins.

All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on

reset. The input buffer must be turned on in the system control block SFS register before

the GPIO input can be read.

7.12.1 Features

• Accelerated GPIO functions:

– GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

– Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

– All GPIO registers are byte and half-word addressable.

– Entire port value can be written in one instruction.

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or

level-sensitive GPIO interrupt request.

• Two GPIO group interrupts can be triggered by any pin or pins in each port.

7.13 AHB peripherals

7.13.1 AES decryption/encryption

The hardware AES engine can decode and encode data using the AES algorithm in

conjunction with a 128-bit key.

The AES encryption and decryption features are accessible through the ROM-based AES

API.

7.13.1.1

Features

• On-chip API support for AES encryption and decryption.

• Two 128-bit OTP memories for AES key storage and customer use.One OTP memory

bank is encrypted.

LPC18S50 Datasheet(PDF) 67 Page - NXP Semiconductors

LPC18S50 Datasheet(HTML) 67 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL