LPC18S50 datasheet(69/151 Pages) NXP

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LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

69 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

• Counters clocked by bus clock or selected input.

• Counters can be configured as up counters or up-down counters.

• State variable allows sequencing across multiple counter cycles.

• Event combines input or output condition and/or counter match in a specified state.

• Events control outputs and interrupts.

• Selected events can limit, halt, start, or stop a counter.

• Supports:

– up to 8 inputs

– up to 16 outputs

– 16 match/capture registers

– 16 events

– 32 states

7.13.3 General-purpose DMA

The DMA controller allows peripheral-to memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receives. The

source and destination areas can each be either a memory region or a peripheral for

master 1, but only memory for master 0.

7.13.3.1

Features

• Eight DMA channels. Each channel can support a unidirectional transfer.

• 16 DMA request lines.

• Single DMA and burst DMA request signals. Each peripheral connected to the DMA

Controller can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the DMA Controller.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers are supported.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority.

• AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.

• Two AHB bus masters for transferring data. These interfaces transfer data when a

DMA request goes active. Master 1 can access memories and peripherals, master 0

can access memories only.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efficiently transfer data.

• Internal four-word FIFO per channel.

• Supports 8, 16, and 32-bit wide transactions.

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