LPC18S50 datasheet(92/151 Pages) NXP

92 / 151 page

LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

92 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

[5]

PLL1 disabled; IRC running; CCLK = 12 MHz.

[6]

VBAT = 3.6 V.

[7]

VDD(IO) = VDDA = 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz.

[8]

VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V. Input leakage increases when VDD(IO) is floating or grounded. It is recommended to keep

VDD(REG)(3V3) and VDD(IO) powered in deep power-down mode.

[9]

On pin VBAT; Tamb =25 C.

[10] Vps corresponds to the output of the power switch (see Figure 9) which is determined by the greater of VBAT and VDD(Reg)(3V3).

[11] VDDA(3V3) = 3.3 V; Tamb =25 C.

[12] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[13] To VSS.

[14] The values specified are simulated and absolute values.

[15] The weak pull-up resistor is connected to the VDD(IO) rail and pulls up the I/O pin to the VDD(IO) level.

[16] The input cell disables the weak pull-up resistor when the applied input voltage exceeds VDD(IO).

[17] The parameter value specified is a simulated value excluding bond capacitance.

[18] For USB operation 3.0 V

 V

DD((IO)  3.6 V. Guaranteed by design.

[19] VDD(IO) present.

[20] Includes external resistors of 33

 1 % on D+ and D.

LPC18S50 Datasheet(PDF) 92 Page - NXP Semiconductors