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LPC18S50 Datasheet(PDF) 82 Page - NXP Semiconductors

Part # LPC18S50
Description  32-bit ARM Cortex-M3 flashless MCU with security features
PDF  151 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC18S50 Datasheet(HTML) 82 Page - NXP Semiconductors

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LPC18S50_S30_S10
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 23 February 2015
82 of 151
NXP Semiconductors
LPC18S50/S30/S10
32-bit ARM Cortex-M3 microcontroller
7.18.9 Power control
The LPC18S50/S30/S10 feature several independent power domains to control power to
the core and the peripherals (see Figure 9). The RTC and its associated peripherals (the
alarm timer, the CREG block, the OTP controller, the back-up registers, and the event
router) are located in the RTC power-domain. The main regulator or a battery supply can
power the RTC. A power selector switch ensures that the RTC block is always powered
on.
The LPC18S50/S30/S10 support four reduced power modes: Sleep, Deep-sleep,
Power-down, and Deep power-down.
The LPC18S50/S30/S10 can wake up from Deep-sleep, Power-down, and Deep
power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery
powered blocks in the RTC power domain.
Fig 9.
LPC18S50/S30/S10 power domains
REAL-TIME CLOCK
BACKUP REGISTERS
RESET/WAKE-UP
CONTROL
REGULATOR
32 kHz
OSCILLATOR
ALWAYS-ON/RTC POWER DOMAIN
MAIN POWER DOMAIN
RTCX1
VBAT
VDDREG
RTCX2
VDDIO
VSS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
OTP
ADC POWER DOMAIN
OTP POWER DOMAIN
USB0 POWER DOMAIN
VDDA
VSSA
VPP
USB0
USB0_VDDA3V3_DRIVER
USB0_VDDA3V3
LPC18xx
ULTRA LOW-POWER
REGULATOR
ALARM
RESET
WAKEUP0/1/2/3
to RTC
domain
peripherals
002aag305
to RTC I/O
pads (Vps)



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