LPC47M182 datasheet(17/223 Pages) SMSC

17 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC LPC47M182

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

PIN#

NAME

(NOTE 1)

DESCRIPTION

BUFFER

NAME

(NOTE 2)

PWR

WELL

(NOTE 3)

NOTES

nRTS1

Active low Request to Send output for the

Serial Port. Handshake output signal

notifies modem that the UART is ready to

transmit data. This signal can be

programmed by writing to bit 1 of the

Modem Control Register (MCR). The

hardware reset will reset the nRTS signal

to inactive mode (high). nRTS is forced

inactive during loop mode operation.

VCC

TXD1

Transmit serial data output.

O12

VCC

nCTS1

Active low Clear to Send input for the

serial port. Handshake signal that notifies

the UART that the modem is ready to

receive data. The CPU can monitor the

status of nCTS signal by reading bit 4 of

Modem Status Register (MSR). A nCTS

signal state change from low to high after

the last MSR read will set MSR bit 0 to a

1. If bit 3 of the Interrupt Enable Register

is set, the interrupt is generated when

nCTS changes state. The nCTS signal

has no effect on the transmitter.

Note: Bit 4 of MSR is the complement of

nCTS.

VCC

nDTR1

(XOR)

Active low Data Terminal Ready output

for the serial port. Handshake output

signal notifies modem that the UART is

ready to establish data communication

link. This signal can be programmed by

writing to bit 0 of Modem Control Register

(MCR). The hardware reset will reset the

nDTR signal to inactive mode (high).

nDTR is forced inactive during loop mode

operation.

XOR Chain Output.

VCC

nRI1

Active low Ring Indicator input for the

serial port. Handshake signal that notifies

the UART that the telephone ring signal is

detected by the modem. The CPU can

monitor the status of nRI signal by

reading bit 6 of Modem Status Register

(MSR). A nRI signal state change from

low to high after the last MSR read will set

MSR bit 2 to a 1. If bit 3 of Interrupt

Enable Register is set, the interrupt is

generated when nRI changes state.

Note: Bit 6 of MSR is the complement of

nRI.

VTR

SERIAL PORT 2 INTERFACE (8)

118

nRI2

Active low Ring Indicator input for serial

port 2. See description for nRI1.

IPD

VTR

6, 10

119

RXD2

Receiver serial data input.

ISPD_400

VCC

120

TXD2

Transmit serial data output.

O12

VCC

LPC47M182 Datasheet(PDF) 17 Page - SMSC Corporation

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