LPC47M182 datasheet(98/223 Pages) SMSC

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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

BIT 0 STROBE - STROBE

This bit is inverted and output onto the nSTROBE output.

BIT 1 AUTOFD - AUTOFEED

This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed

after each line is printed. A logic 0 means no autofeed.

BIT 2 nINIT - INITIATE OUTPUT

This bit is output onto the nINITP output without inversion.

BIT 3 SLCTIN - PRINTER SELECT INPUT

This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0

means the printer is not selected.

BIT 4 IRQE - INTERRUPT REQUEST ENABLE

The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the

Parallel Port to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK

input. When the IRQE bit is programmed low the IRQ is disabled.

BIT 5 PCD - PARALLEL CONTROL DIRECTION

Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out

regardless of the state of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port

is in output mode (write); a logic 1 means that the printer port is in input mode (read).

Bits 6 and 7 during a read are a low level, and cannot be written.

7.4.4

EPP ADDRESS PORT

ADDRESS OFFSET = 03H

The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register is

cleared at initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-

DB7 are buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an

EPP ADDRESS WRITE cycle to be performed, during which the data is latched for the duration of the EPP

write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP

ADDRESS READ cycle to be performed and the data output to the host CPU, the deassertion of

ADDRSTB latches the PData for the duration of the read cycle. This register is only available in EPP

mode.

7.4.5

EPP DATA PORT 0

ADDRESS OFFSET = 04H

The EPP Data Port 0 is located at an offset of ‘04H’ from the base address. The data register is cleared at

initialization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are

buffered (non inverting) and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP

DATA WRITE cycle to be performed, during which the data is latched for the duration of the EPP write

cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP READ

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