LPC47M182 datasheet(96/223 Pages) SMSC

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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

Table 7.1 - Parallel Port Connector

HOST

CONNECTOR

SMSC

PIN NUMBER

STANDARD

EPP

ECP

nSTROBE

nWrite

nStrobe

2-9

PD<0:7>

PData<0:7>

nACK

Intr

nAck

BUSY

nWait

Busy, PeriphAck(3)

(User Defined)

PError,

nAckReverse (3)

SLCT

(User Defined)

Select

nALF

nDatastb

nAutoFd,

HostAck(3)

nERROR

(User Defined)

nFault (1)

nPeriphRequest (3)

nINITP

nRESET

nInit(1)

nReverseRqst(3)

See section Chapter

3 Description of Pin

Functions.

nSLCTIN

nAddrstrb

nSelectIn(1,3)

(1) = Compatible Mode

(3) = High Speed Mode

Note:

For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the

IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This

document is available from Microsoft.

7.4

IBM XT/AT Compatible, Bi-Directional and EPP Modes

7.4.1

DATA PORT

ADDRESS OFFSET = 00H

The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at

initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal

data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.

During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host

CPU.

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