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LPC47M182 Datasheet(PDF) 29 Page - SMSC Corporation |
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LPC47M182 Datasheet(HTML) 29 Page - SMSC Corporation |
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29 / 223 page  Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC LPC47M182 29 Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05) DATASHEET Chapter 4 Block Diagram LPC47M182 (128 QFP) DIGITAL DATA SEPARATOR WITH WRITE PRECOM- PENSATION SMSC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE WDATA WCLOCK RCLOCK RDATA FAN Monitoring Power LED Multi-Mode Parallel Port with ChiProtectTM PD[7:0] BUSY, SLCT, PE, nERROR, nACK nSTROBE, nINITP, nSLCTIN, nALF Internal Bus (Data, Address, and Control lines) High-Speed 16550A UART PORT RXD nDSR nRI nCTS nIO_PME GPIOs GP10-GP15, GP16*, GP17* (GP20-GP23)* LAD[3:0] nLFRAME nLDRQ nPCI_RESET nLPCPD SER_IRQ PCI_CLK LPC Bus Interface SERIAL IRQ / Interrupt Generating Registers XOR-Chain KCLK, MCLK KDAT, MDAT GA20M nKBDRST nFPRST nSECONDARY_HD nPCI_RST_OUT nPCI_RST_OUT2 F_CAP V_5P0_STBY nRSMRST REF5V REF5V_STBY nAUD_LINK_RST nCDC_DWN_ENAB* nCDC_DWN_RST nHD_LED nSCSI nIDE_RSTDRV nPRIMARY_HD Note 1: This diagram shows the various functions available on the chip (not pin layout). The block diagram should not be used for pin count. Note 2: Functions with asterisks (*) are located on multifunctional pins. PME / Power Control LATCHED_BF_CUT nPS_ON SCK_BJT_GATE nBACKFEED_CUT PWRGD_PS TXD nRTS nDTR* nDCD nPCI_RESET CNR Logic Hard Drive Front Panel LED Power Sequencing VGA Voltage Translation SMBus Isolation CLOCK GEN Configuration Registers Keyboard/Mouse 8042 Controller VCC (3.3V) VTR (3.3V) V_5P0_STBY Buffered PCI Reset GP24* Resume Reset Generation 5V Reference Generation High-Speed 16550A UART PORT 2 W/ Infrared nDSR2 nRI2 nCTS2 nRTS2 nDCD2 RXD2 TXD2 nDTR2 IRTX2 IRRX2 Figure 4.1 – LPC47M182 Block Diagram |
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