LPC47M182 datasheet(5/223 Pages) SMSC

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Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

SMSC LPC47M182

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

DATASHEET

7.3

Parallel Port....................................................................................................................................... 95

7.4

IBM XT/AT Compatible, Bi-Directional and EPP Modes...................................................................96

7.4.1

DATA PORT ...........................................................................................................................................96

7.4.2

Status Port..............................................................................................................................................97

7.4.3

CONTROL PORT ...................................................................................................................................97

7.4.4

EPP ADDRESS PORT ...........................................................................................................................98

7.4.5

EPP DATA PORT 0 ................................................................................................................................98

7.4.6

EPP DATA PORT 1 ................................................................................................................................99

7.4.7

EPP DATA PORT 2 ................................................................................................................................99

7.4.8

EPP DATA PORT 3 ................................................................................................................................99

7.5

EPP 1.9 Operation ............................................................................................................................ 99

7.5.1

Software Constraints ..............................................................................................................................99

7.6

EPP 1.9 Write..................................................................................................................................100

7.7

EPP 1.9 Read..................................................................................................................................100

7.8

EPP 1.7 Operation ..........................................................................................................................101

7.8.1

Software Constraints ............................................................................................................................101

7.9

EPP 1.7 Write..................................................................................................................................101

7.10

EPP 1.7 Read ..............................................................................................................................101

7.10.1

Extended Capabilities Parallel Port ...................................................................................................102

7.10.2

Vocabulary ........................................................................................................................................102

7.11

ECP Implementation Standard ....................................................................................................103

7.11.1

Description ........................................................................................................................................103

7.12

Register Definitions ......................................................................................................................104

7.12.1

DATA and ecpAFifo PORT ...............................................................................................................105

7.12.2

DEVICE STATUS REGISTER (dsr) ..................................................................................................106

7.12.3

DEVICE CONTROL REGISTER (dcr)...............................................................................................106

7.12.4

CFIFO (Parallel Port Data FIFO).......................................................................................................107

7.12.5

ECPDFIFO (ECP Data FIFO)............................................................................................................107

7.12.6

tFifo (Test FIFO Mode)......................................................................................................................107

7.12.7

cnfgA (Configuration Register A).......................................................................................................108

7.12.8

cnfgB (Configuration Register B).......................................................................................................108

7.12.9

ecr (Extended Control Register)........................................................................................................108

7.13

Operation .....................................................................................................................................110

7.13.1

Mode Switching/Software Control .....................................................................................................110

7.14

ECP Operation .............................................................................................................................110

7.15

Termination from ECP Mode .......................................................................................................111

7.16

Command/Data ............................................................................................................................111

7.17

Data Compression .......................................................................................................................111

7.18

Pin Definition ................................................................................................................................112

7.19

LPC Connections .........................................................................................................................112

7.20

Interrupts ......................................................................................................................................112

7.21

FIFO Operation ............................................................................................................................112

7.21.1

DMA TRANSFERS ...........................................................................................................................113

7.21.2

DMA Mode - Transfers from the FIFO to the Host ............................................................................113

7.21.3

Programmed I/O Mode or Non-DMA Mode.......................................................................................113

7.21.4

Programmed I/O - Transfers from the FIFO to the Host....................................................................114

7.21.5

Programmed I/O - Transfers from the Host to the FIFO....................................................................114

7.22

Power Management.....................................................................................................................114

7.23

Serial IRQ.....................................................................................................................................114

7.23.1

Timing Diagrams For SER_IRQ Cycle ..............................................................................................115

7.23.2

SER_IRQ Cycle Control....................................................................................................................115

7.23.3

SER_IRQ Data Frame ......................................................................................................................116

7.23.4

Stop Cycle Control ............................................................................................................................117

7.23.5

Latency .............................................................................................................................................117

7.23.6

EOI/ISR Read Latency......................................................................................................................117

7.23.7

AC/DC Specification Issue ................................................................................................................117

7.23.8

Reset and Initialization ......................................................................................................................117

7.24

Interrupt Generating Registers.....................................................................................................117

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