LPC47M182 datasheet(76/223 Pages) SMSC

76 / 223 page

Advanced I/O Controller with Motherboard GLUE Logic

Datasheet

Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)

SMSC LPC47M182

DATASHEET

When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to

“0” (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to “1” for that

drive to be set automatically to Perpendicular mode. In this mode the following set of conditions also

apply:

The GAP2 written to a perpendicular drive during a write operation will depend upon the programmed

data rate.

The write pre-compensation given to a perpendicular mode drive will be 0ns.

For D0-D3 programmed to “0” for conventional mode drives any data written will be at the currently

programmed write pre-compensation.

Note: Bits D0-D3 can only be overwritten when OW is programmed as a “1”.If either GAP or WGATE is a

“1” then D0-D3 are ignored.

Software and hardware resets have the following effect on the PERPENDICULAR MODE COMMAND:

“Software” resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to “0”. D0-D3

are unaffected and retain their previous value.

“Hardware” resets will clear all bits (GAP, WGATE and D0-D3) to “0”, i.e all conventional mode.

LPC47M182 Datasheet(PDF) 76 Page - SMSC Corporation