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MFC2000 Datasheet(PDF) 24 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 24 Page - List of Unclassifed Manufacturers |
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24 / 426 page ![]() MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 3-4 Conexant 100723A Table 3-1. Pin Description (4 of 6) Pin Name Pin No. I/O Input Type Output Type Pin Description SLCTOUT C3 O - 2XT3V PIO Returned status to PC PE B2 O - 2XT3V PIO Returned status to PC FAULTn B1 O - 2XT3V PIO Returned status to PC (active low) PIOD[7:0] D2,D1,C2,H4,H 3,H2,H1,G4 I/O H5VT 2XT5VT (Hysteresis) Driven by PC or MFC2000 and used to send data or address depending on which mode is used TESTER_MODE J2 I HD5VT - (Hysteresis) For test only, It must be ‘low’ for the normal operation ADCREFp Y3 I Positive reference voltage for the scan PADC ADCREFn Y2 I Negative reference voltage for the scan PADC POWER1 Y1 I Voltage input for power-down detection circuit 1 POWER2 W4 I Voltage input for power-down detection circuit 2 ADGA Y5 - Scan PADC analog ground ADVA V5 - Scan PADC analog Power ADGD U5 - Scan PADC digital ground SDAA_SPKR V12 O Analog telephone line monitoring output from SSD ADCV Y4 - Scan PADC internal ground SCIN W5 I Analog scan input signal SENIN[2:0] V6,W6,Y6 I Analog sensor inputs for TADC TCK W3 I HD5VT - (Hysteresis, Pull down) Test clock input for JTAG. It is positive edge-triggered. TMS W2 I HU5VT - (Hysteresis, Pull up) Test mode select input for JTAG. Selects the next state in the TAP state machine. TRSTn W1 I HD5VT - (Hysteresis, Pull down) Suggestion by Lauterbach for JTAG: connect this signal to RESETn in normal mode and disconnect in debug mode. TDI V4 I HU5VT - (Hysteresis, Pull up) Test data input for JTAG. Serial data input to the JTAG shift register. TDO V3 O - 1XT5VT Test data output for JTAG. Serial data output from the JTAG shift register. TEST V2 I HD5VT - (Hysteresis, Pull down) For test only, It must be ‘low’ for the normal operation. SCANMOD J1 I HD5VT - (Hysteresis, Pull down) For the scan test only, It must be ‘low’ for normal operations. P80_SEL J3 I H3V - P80 DSP test and DFT scan mode select, This pin is only used for the test mode. PLLREF_XIN Y15 I OSC - Crystal input pin for PLL PLLREF_XOUT W15 O - OSC Crystal output pin for PLL PLLVDD U15 - +3.3V digital power for PLL PLLVSS U16 - +3.3V digital ground for PLL SDDATA[15:0] N20,P17,P18,P 19,P20,R17,R1 8,R19,R20,T17, T18,T19,T20,U1 7,U18,U19 I/O 5VT 2XT5VT Countach (S)DRAM data bus (16 bits) |
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