MFC2000 datasheet(54/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-24

Conexant

100723A

4.3

SIU

4.3.1

Functional Description

The System Integration Unit (SIU) is responsible for interfacing between the ARM7TDMI core, the Cache Memory

Controller, the Internal Peripheral Bus (IPB), and the External Bus (EB). The ARM7TDMI core and the Cache

Memory Controller are on the Internal System Bus (ISB). The ISB data bus is 32-bits wide and the IPB and EB

data buses are 16-bits wide. The SIU generates the external chip selects along with chip selects to all the internal

peripherals. It provides the following functions:

Interfaces between the Internal Peripheral Bus (IPB), the Internal System Bus (ISB) and the External Bus

(EB). The SIU allows bus master devices on the IPB and ISB.

Control the chip selects to devices on the IPB, the ISB, and the EB.

Address multiplexing for DRAM access.

ROM interleave control (including wait state control for the interleave mode): no interleave and 2-way

interleave with external Q-switch.

Fast page mode ROM operation.

Even though ARM7TDMI is fixed to the little endian in this MFC2000 chip, the SIU can support the little

endian or big endian for the DMA operation.

Support Arm and Thumb mode operations.

4.3.1.1

IPB, ISB and External Bus

IPB Bus

The IPB Bus supports both 8-bit and 16-bit peripherals. The ARM or an internal bus master such as DMA can

access a device residing on the IPB bus.

The SIU provides the chip selects to each of the internal peripheral devices. The chip selects are driven in the

second clock cycle of an IPB bus cycle. The peripheral device needs to decode only the address lines required to

access the specific registers within the block.

Transactions on the IPB bus only occur when a device on the IPB bus is being accessed. All accesses on the IPB

bus require two peripheral bus clock cycles (2 SIUCLK’s). During the first cycle, the address is decoded and

determined if an access to an internal peripheral is occurring. During the second cycle the peripheral chip select is

asserted, and the access occurs.

During Write operations to peripherals, signals BS[1:0] are used to signal which bytes are valid on the data bus.

8-bit peripherals can ignored these signals. 16-bit peripherals MUST use these signals to allow each 8-bit half of

the peripheral registers to be written independently. This is due to the fact that the ARM compiler may generate

two byte transactions when accessing a 16-bite register on the IPB instead of a single halfword transaction.

During Read operations, the peripherals must fill the 16-bit IPB data bus. If the peripheral is less than 16-bit wide,

it should fill the empty bits with 0.

MFC2000 Datasheet(PDF) 54 Page - List of Unclassifed Manufacturers

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