MFC2000 datasheet(94/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-64

Conexant

100723A

Refresh

Speed:

(bit 5)

Oscillator

Speed:

(bit 4)

Refresh

Speed:

Description:

normal

RTC crystal frequency = 32.768 kHz,

Refresh clock = the crystal frequency = 32.768 kHz,

The refresh cycle time = 15.625 ms/1024 cycles.

fast

RTC crystal frequency = 65.536 kHz,

Refresh clock = the crystal frequency = 65.536 kHz,

Refresh cycle time = 7.8125 ms/1024 cycles.

slow

RTC crystal frequency = 32.768 kHz,

Refresh clock = the crystal frequency/8 = 4.096 kHz

Refresh cycle time = 125 ms/1024 cycles.

slow

RTC crystal frequency = 65.536 kHz,

Refresh clock = the crystal frequency/16 = 4.096 kHz

Refresh cycle time = 125 ms/1024 cycles.

Bits 3:

Bank 1 Enable

This bit controls whether or not the Bank 1 DRAMs will be enabled.

The Enable signal will allow CAS before RAS refresh to occur based

on the non-interleave or interleave setting. If the bank setting indicates

a non-interleaved mode, RASn[1] and CASOn[0] (8-bit mode) or

CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting

indicates an interleaved mode, RASn[1], CASOn[1:0] and CASEn[1:0]

will refresh the DRAM. DWRn will be high during refresh. If bank 1 is

disabled, RAS[1]n will be tri-stated and all appropriate CASn’s will be

tri-stated based on mode settings.

Bit 2:

Bank 0 Enable

This bit controls whether or not the Bank 0 DRAMs will be enabled.

The Enable signal will allow CAS before RAS refresh to occur based

on the non-interleave or interleave setting. If the bank setting indicates

a non-interleaved mode, RASn[0] and CASOn[0] (8-bit mode) or

CASOn[1:0] (16-bit mode) will refresh the DRAM. If the bank setting

indicates an interleaved mode, RASn[0], CASOn[1:0] and CASEn[1:0]

will refresh the DRAM. DWRn will be high during refresh. If bank 0 is

disabled, RAS[0]n will be tri-stated and all appropriate CASn’s will be

tri-stated based on mode settings.

Bit 1:

Bank 1 Interleave Enable

This register defines whether the bank 1 DRAMs are to be accessed

using 2-way interleave or non interleaved access. 2-way interleaved

access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface

size bit for bank 1 is ignored by the DRAM controller, but is used by

the SIU to output the data correctly).

Bit 0:

Bank 0 Interleave Enable

This register defines whether the bank 0 DRAMs are to be accessed

using 2-way interleave or non interleaved access. 2-way interleaved

access is only valid with a 16-bit interface (the 16 bit vs. 8 bit interface

size bit for bank 1 is ignored by the DRAM controller, but is used by

the SIU to output the data correctly).

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