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MFC2000 Datasheet(PDF) 86 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 86 Page - List of Unclassifed Manufacturers |
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86 / 426 page ![]() MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4-56 Conexant 100723A 4.5.1.2 Non-Interleaved DRAM Accesses Non-interleaved DRAM accesses are available for 8-bit or 16-bit data bus. Byte access is available for both 8-bit and 16-bit data bus and 16-bit halfword access is available for 16-bit data bus. DRAM early-write mode, normal read mode and page mode are supported. Read-modify-write is not supported. Note: 16-bit DRAMs must have upper and lower CAS’s in order to work with the DRAM controller. 8-bit bursts of data will not work with a 16-bit wide memory structure. 03000000h 02000000h 04000000h 03400000h Bank 0 Bank 1 NOTE: In this example, Bank 0 is 8M and Bank 1 is 4M. 02800000h RASn[0] RASn[1] Figure 4-15. DRAM Bank/Address Map 4.5.1.3 2-way Interleaved DRAM Accesses The two-way interleaved DRAM interface can support up to four 16-bit wide devices a maximum of 8M deep. Bank 0 is selected with RASn[0] and bank 1 is selected with RASn[1]. CASEn[1:0], CASOn[1:0], DWRn, DOEOn, DOEEn, ADDR, and DATA are common between the two banks. 2-way interleaving is limited to a 16-bit wide databus. 8-bit or 16-bit wide devices can be used. The ARM CPU can write 32-bit words, 16-bit halfwords or bytes to the memory banks. The addressing to the interleaved DRAMs starts with address bit 2. Bits 1 and 0 are used internally to generate the proper CASOn[1:0] and CASEn[1:0] signals. When the memory structure is configured for two-way interleaving, byte bursts are not allowed. Only bursts of 32-bit words or 16-bit halfwords are allowed. The maximum burst length is eight 16-bit halfwords. The burst length is controlled by the DRAMBURST signal that is sent from the SIU. The external memory structure can use the output enables directly to the memory device or for increased speed can use external bus transceivers. Bus contention must be considered when the output enables are tied directly to a DRAM memory. |
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