MFC2000 datasheet(57/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-27

Table 4-5. Access Modes for Reading ROM

ROM Access

Mode

Data Type

Cache Memory

Wait States

Notes

8-bit non-

interleave

instruction

Cache enabled

and Cache miss

w,w,w,w,w,w,w,w

(16 sequential accesses)

This is cache burst access. Save the address decoding

cycle for all accesses except the first access.

16-bit non-

interleave

instruction

Cache enabled

and Cache miss

w,w,w,w,w,w,w,w

(8 sequential accesses)

This is cache burst access. Save the address decoding

cycle for all accesses except the first access.

8-bit non-

interleave

instruction

Cache disabled

If the sequential access occurs, save the address decoding

cycle for all accesses except the first access.

16-bit non-

interleave

instruction

Cache disabled

If the sequential access occurs, save the address decoding

cycle for all accesses except the first access.

8-bit non-

interleave

data

Not applied

If the sequential access occurs, save the address decoding

cycle for all accesses except the first access.

16-bit non-

interleave

data

Not applied

If the sequential access occurs, save the address decoding

cycle for all accesses except the first access.

16-bit 2-way

interleave

instruction

Cache enabled

and Cache miss

w, s,

w-s-1, s,

w-s-1, s

(8 sequential accesses)

This is cache burst access. 0 or 1 wait state is

programmable and depends on the CPU clock frequency

and the ROM speed. If ‘w-s-1’ is less than 1, it will be forced

to 1.

16-bit 2-way

interleave

instruction

Cache disabled

w, s,

w-s-1, s,

w-s-1, s

(one interleave access

sequence)

The actual sequential

access length is dynamic.

0 or 1 wait state is programmable and depends on the CPU

clock frequency and the ROM speed. If the starting address

of the sequential access is not lined up with the octal

address boundary of the interleave access, the partial

interleave access sequence should be done. Then, restart

the interleave access sequence at the octal address

boundary of the interleave access. Even if the stopping

address of the sequential access is not lined up with the

octal address boundary of the interleave access, the access

sequence must be stopped immediately at anywhere. If ‘w-

s-1’ is less than s, it will be forced to s.

16-bit 2-way

interleave

data

Cache enabled

and Cache miss

w, s,

w-s-1, s,

w-s-1, s

(one interleave access

sequence)

The actual sequential

access length is dynamic.

0 or 1 wait state is programmable and depends on the CPU

clock frequency and the ROM speed. If the starting address

of the sequential access is not lined up with the octal

address boundary of the interleave access, the partial

interleave access sequence should be done. Then, restart

the interleave access sequence at the octal address

boundary of the interleave access. Even if the stopping

address of the sequential access is not lined up with the

address boundary of the interleave access, the access

sequence must be stopped immediately at anywhere. If ‘w-

s-1’ is less than s, it will be forced to s.

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