MFC2000 datasheet(92/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-62

Conexant

100723A

Bit 4:

Bank 0 Increase RAS Cycle Time

This register will add one cycle after the refresh cycle prior to RAS

precharge to meet TRC (RASn cycle time). This is needed in order to

use 70 ns DRAMs while running at 39MHz.

Bit 3:

Bank 0 2-cycle RAS Precharge

This register will increase the RASn[0] Precharge time from 1 to 2

clock cycles.

Bit 2:

Bank 0 1-cycle RAH

This register will increase the RASn[0] address hold time. When this

bit is set, the address will be multiplexed 1 clock cycle after the falling

edge of RAS[0]n. The default setting will multiplex the row/column

address ½ clock cycle after the falling edge of RAS[1]n.

Bits 1-0:

Bank 0 Speed Control

These registers will control the speed of the DRAM interface for bank

0 when in the non-interleaved mode. This register controls the width of

the CASn signal. These bits are ignored in interleaved mode.

Bit 1

Bit 0

Non-Interleaved Operation

CASn is ½ clock cycle wide.

CASn is 1 clock cycle wide.

CASn is 2 clock cycles wide for Read

and 1 clock cycle wide for write.

N/A

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Backup

Configuration

(BackupConfig)

$01FF8099

(Not Used)

Internal

Power Down

Select

Batrstn

Detected

Lockenn

Timeout

Detected

SRAM

Enable

0 = disable

1 = enable

Bank 1

Data

interface

size:

0 = 8-bit

1 = 16-bit

Bank 0

Data

interface

size:

0 = 8-bit

1 = 16-bit

Rst. Value

xxxxx000b

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Backup

Configuration

(BackupConfig)

$01FF8098

DRAM Backup Time

0 = no backup

1 = 1-2 days

2 = 2-3 days

3 = infinite days

Refresh

Rate

0 = normal

1 = slow

Oscillator

Speed

0 =

32.768 kHz

1 =

65.536 kHz

Bank 1

Enable

0 = disable

1 = enable

Bank 0

Enable

0 = disable

1 = enable

Bank 1

Interleave

Enable

0 = non

interleaved

1 = 2 way

interleaved

Bank 0

Interleave

Enable

0 = non

interleaved

1 = 2 way

interleaved

Rst. Value

00h

Read Value

00h

RTC Battery during power down. When a time out condition occurs, the RASn and CASn signals are tri-stated.

When prime power has returned from a power down sequence, the user will have to perform a checksum on the

DRAM data to know if a time out has occurred since there is no indication that the DRAM battery has lost power.

The user will have to wait 1ms before accessing the DRAM after prime power has returned.

Bits 15-14:

Not used

Bit 13:

Internal Power Down Select

0 = PWRDWNn is generated by or-ing power_down1 with

power_down2

1= PWRDWNn is generated by and-ing power_down1 with

power_down2

MFC2000 Datasheet(PDF) 92 Page - List of Unclassifed Manufacturers

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