MFC2000 datasheet(84/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-54

Conexant

100723A

4.4.3

Timing

SIUCLK

(internal)

MIRQn

PRTIRQn(IRQ2)

GPIO[8](IRQ11)

GPIO[9](IRQ13)

IRQ16(SYSIRQ)

Figure 4-14. External Interrupt Request Timing

Note:

The MFP2000 chip resynchronizes MIRQn,

PRTIRQn, GPIO[8], GPIO[9], and

IRQ16 signals internally. There are no setup time and hold time requirements for MIRQn,

PRTIRQn,

GPIO[8], GPIO[9], MIRQn, and IRQ16 signals with respect to SYSCLK. The four

external interrupts PRTIRQn, GPIO[8], GPIO[9], and IRQ16 can also be programmed as edge

triggered interrupts. In this case, the interrupt signals are implemented as clock into flip-flops

with D-input either tied to high or low; again there is no setup and hold time requirements either.

4.5

DRAM Controller (Including Battery DRAM)

4.5.1

Functional Description

The DRAM Controller interfaces to external memory devices and to the internal ARM7 SIU block. The DRAM

memory space can be divided into two banks of memory which can be independently configured. The system

clock rate that is supported can be up to 40MHz and can support the DRAM characteristics that are listed in the

following tables

Addressing Size:

512K, 1M, 4M, 16M

Organization:

4 bits, 8 bits, or 16 bits

Access Speed:

50, 60, 70, 80 ns

The maximum memory size that is supported for two memory banks is 32M. The DRAM Chip sizes that are

supported go up to 16M, but are limited to the row/column configurations that can be accommodated from the

address multiplexing table (Table 4-12) and the DRAM row/column configuration Table 4-14).

The number of DRAM access and refresh cycle wait states can be programmed from the DRAMCtrl register.

Specifically, options to control the RAS precharge width, RAS low time, and CAS low time are provided. The drive

capability of the DRAM control signals can support a maximum of 50pF of loading capacitance.

Several types of external DRAM configurations can be supported: non-interleaved (8-bit or 16-bit data bus) and 2-

way interleaved (16-bit data bus) (See Table 4-11). Memory bank 0 can be configured independently from

memory bank 1.

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