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MFC2000 Datasheet(PDF) 81 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 81 Page - List of Unclassifed Manufacturers |
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81 / 426 page ![]() Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 4-51 4.4.2.4 IRQ Enable2 Register Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: IRQEnable2 0x01FF8027 (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) Rst Value xxh Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: IRQEnable2 0x01FF8026 (Not Used) Enable IRQ22 irqusb Enable IRQ21 irqtimer2 Enable IRQ20 irqsdaa Enable IRQ19 irqdma5 Enable IRQ18 irqssif Enable IRQ17 irqsw Enable IRQ16 irqsys Rst Value x0000000b Read Value 00h Bit 3 – 0: When 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. R/W. 4.4.2.5 FIQ Enable1 Register Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: FIQEnable1 0x01FF8029 Enable IRQ15 irqsopif Enable IRQ14 irqt4 Enable IRQ13 irqext2 Enable IRQ12 irqpio Enable IRQ11 irqext1 Enable IRQ10 irqtimer1 Enable IRQ9 irqvsc Enable IRQ8 irqdma10 Rst Value 00h Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: FIQEnable1 0x01FF8028 Enable IRQ7 irqbrc Enable IRQ6 irqdma2 Enable IRQ5 irqsasif Enable IRQ4 irqvpstep Enable IRQ3 irqsstep Enable IRQ2 irqprt Enable IRQ1 irqcss Enable IRQ0 MIRQ Rst Value 00h Read Value 00h Bit 15 – 0: When 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. R/W. 4.4.2.6 FIQ Enable2 Register Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: FIQEnable2 0x01FF802B (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) (Not Used) Rst Value xxh Read Value 00h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: FIQEnable2 0x01FF802A (Not Used) Enable IRQ22 irqusb Enable IRQ21 irqtimer2 Enable IRQ20 irqsdaa Enable IRQ19 irqdma5 Enable IRQ18 irqssif Enable IRQ17 irqsw Enable IRQ16 irqsys Rst Value x0000000b Read Value 00h Bit 3 – 0: When 1 will enable the corresponding interrupt and when 0 will mask that interrupt out. R/W. |
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