MFC2000 datasheet(75/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-45

Table 4-8. Read/Write with Wait States Timing Parameters

Parameter

Symbol

Min.

Max.

Units

Address delay time

Chip select delay time

CSD

Read delay time for the normal case and delay-on)

Write delay time (the normal case, delay-on, and early-off)

CS[4:3] delay time (gated with read or write strobe)

CGD

Data input setup time

DIS

Data input hold time

DIH

Data output delay time

DOD

Data output hold time

DOH

Read delay time (for zero wait state)

R0D

Write delay time (for zero wait state)

W0D

CS[4:3] delay time (gated with read or write strobe for zero wait state)

CG0D

Data input setup time (for zero wait state)

DI0S

Data input hold time (for zero wait state)

DI0H

Data output delay time (for zero wait state)

DO0D

Data output hold time (for zero wait state)

DO0H

2-way interleave address delay time

IAD

ALE address setup time

AAD

ALE address hold time

AAH

ALE delay time

Iald

Address setup time (read and write)

IAS

Address hold time (read and write)

IAH

Data hold time (write)

IDH

Note:

SIUCLK is the internal system interface clock. These values are for SIUCLK = 30 MHz.

When S=0 in the 2-way interleave read operation, tIAD parameter is still same.

4.3.4

Firmware Operation

Caution

Only word or half-word accesses that happen on their respective boundaries are

valid. If the access is to a non-boundary address, the SIU ignores the last 2 LSBs (word access)

or 1 LSB (half word access) and reset the address to the appropriate boundaries.

For 16-bit register, writing a byte to the even address (register address) will update the lower 8-bits of the register.

Writing a byte to the odd address (register address + 1) will update the upper 8 bits of the register. BS[1:0]

indicate which byte is written. Writing a halfword to either the even or odd address will update all 16-bits.

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