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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-68

Conexant

100723A

The timing diagram illustrates two-way interleaved DRAM write. This configuration assumes that the data bus is

available to the DRAM with enough setup time to the CASn falling edge. In addition, this configuration has a 2-

cycle wide RASn and allows one cycle after the falling edge of RASn before the row/column address mux.

SIUCLK

RASn[1]

CASEn[1:0]

DWRn

CASOn[1:0]

tRP

tRAS

a refresh cycle

tCP

Figure 4-24. Refresh Cycle

The timing diagram illustrates a refresh cycle. tRAS is three cycles wide to accommodate frequency ranges up to

40 MHz. This timing is used during prime power refresh. During battery backup, a custom refresh circuit is used to

generate refreshed timing based on the oscillator clock.

4.5.4

Detailed Timing Measurements

Access with 1 or

2 wait states

Access with

0 wait states

SIUCLK

RASN[1:0]

CASEN[1:0],

CASON[1:0]

DWRN

(write)

CD0

COL

A[x:0]

(option 1)

ROW

COL

A[x:0]

(option 2)

RAH1

RAH2

CSU

CSU0

DWRN

(read)

CDO

Note:1

Note:2

ROW

Figure 4-25. DRAM Timing



Read, Write and Wait States for Non-interleave Mode

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