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MFC2000 Datasheet(PDF) 101 Page - List of Unclassifed Manufacturers |
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MFC2000 Datasheet(HTML) 101 Page - List of Unclassifed Manufacturers |
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101 / 426 page  Hardware Description MFC 2000 Multifunctional Peripheral Controller 2000 100723A Conexant 4-71 Table 4-15. DRAM Timing Parameters Parameter Symbol Min. Max. Units RASN delay t RD 20 ns CASN delay (0 wait state) t CD0 20 ns CASN delay t CD 20 ns CASN address setup (0 wait state) (10Mhz) t CSU0 7 ns CASN address setup (30 MHz) t CSU 7 ns RASN address hold 1 t RAH1 3 ns RASN address hold 2 t RAH2 3 ns DWRN delay t DW 20 ns OE delay t OED 20 ns CASN pulse width t RCAS 30 500 ns RASN pulse width t RRAS 30 500 ns CASN to RASN delay t CRD 5 200 ns Notes: 1. Bit 2 of the DRAM Control Register sets this time to ½ or 1 clock cycle. 2. Bit 8 and 9 of the DRAM Control Register sets this time to 1 or 2 clock cycles. 4.5.5 Software Operation Special Cautions • The Backup Configuration register is set to 0000h the initial power up only. This register is backed up during battery power mode. • DRAM control signals are tri-stated during battery power if the backup timer is set to 0 or the backup time expires, regardless of how the enable bits are set. • After a reset occurs and the CPU is released to run, the CPU cannot write to the Backup Configuration register until one OSCCLK cycle has passed. • During power-up, the firmware must pay attention to the power up DRAM requirements specified in the DRAM data books. Typically, DRAMs cannot be accessed for 200 µs and then must have 8 CASn before RASn refreshes occur before accessing the DRAMs. • Within the DRAM Memory address space memory bank mirroring is allowed. Firmware will have to determine the memory size. |
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