MFC2000 datasheet(96/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-66

Conexant

100723A

The timing diagram illustrates a 16-bit memory data bus, a burst of word transfers (2 words) from the ARM7 for

full clock width CASn and PG = one wait state (non-interleaved). It also illustrates that the octal halfword boundary

doesn’t occur in the middle of the burst of word transfers.

SIUCLK

RASn[0]

CASEn[0]

DWRn

ARM ADDR

or DMA ADDR

SIU ADDR

EXT ADDR

ROW

COL

DATA

DOEEn

data

Figure 4-20. CASn Non-Interleaved 8-bit DRAM Read

The timing diagram illustrates a two clock cycle CASn non-interleaved 8-bit DRAM read (Non burst mode). This

configuration illustrates the row/column address multiplex occurring 1 cycle after RASn.

SIUCLK

RASn[0]

CASEn[1:0]

DWRn

ARM ADDR

or DMA ADDR

SIU ADDR

EXT ADDR

ROW

COL

DATA

DOEOn

DOEEn

CASOn[1:0]

SIU P_ADDR

COL

+10

NOTE: In this example, a[2:0] = 00x. Also, the external address is created from the pipelined

SIU address; however, address pins a1 and a0 are not connected to the external memories.

Figure 4-21. 2-Way Interleaved Memory with Halfword Bursts of Data

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