MFC2000 datasheet(34/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-4

Conexant

100723A

Table 4-1. Fixed-Location and Size Chip Selects

Chip Select

Device

ROMCSn

ROM

FCS1n/FCS0n

NAND- or NOR-type Flash Memory

CS0n

SRAM, or other

CS1n (Optional)

General Use

Optional MCSn (Optional)

External Fax Modem (optional)

CS2n

I/O Devices, or other

CS3n (Optional)

General Use

CS4n (OptionaL0

General Use

CS5n

4 MB ROM, SRAM, or other

DRAM/ARAM chip selects can also be programmed to 1 of 4 sizes (from 512 k to 16 M).

ROM Chip Select (ROMCSn)

ROMCSn selects external ROM located in 4-MB address space 00000000h-003FFFFFh, and is active for read

and write accesses. The ROMCtrl register can be used to select 0 to 7 (default) wait states, and 0 or 1 (default)

read and write strobe on delays. For customers that choose to use NOR-type flash memory in the ROM address

area, the write operation is also allowed in the ROM address area.

Chip Select 5 (CS5n)

CS5n is an active Read/Write select signal for the 4 MB address range (00400000h to 007FFFFFh) directly below

the ROMCSn address range. The CS5Ctrl register can be used to select 0 to 7 (default) wait states, and 0 or 1

(default) read and write strobe on delays. GPIO[7] (default) can be configured as CS5n using the GPIO[7]/CS5n

bit of the GPIOConfig register.

SRAM Chip Select 0 (CS0n)

CS0n is designed for use in selecting external SRAM, but can also be used for other purposes. It has 2 MB

address range (00E00000h to 00FFFFFFh). The CS0n can also be programmed for 0 (default) to 7 wait states, 0

(default) or 1 read and write strobe on delays, and normal (default) or early write strobe off times using the

CS0Ctrl register.

DRAM Chip Select (RASn[1:0], CASOn[1:0] and CASEn[1:0])

DRAM address space can be selected in 2 separate memory blocks (Bank 0: RASn[0] and Bank 1: RASn[1]).

Separate control bits are provided in the Backup Configuration register to enable and disable each of the memory

banks (Default: Bank0 is enabled and 8-bit DRAM is selected). Non-interleaved DRAM accesses and 2-way

interleaved DRAM accesses are supported. CASOn[1:0] and CASEn[1:0] are used differently for different access

modes. RASn is asserted before CASn for normal read and write operations. Also, RAS can be kept active and

CASn is toggled to do burst mode operations. CASn-Before-RASn refresh mode is the only refresh mode for

MFC2K (For more DRAM information, see the DRAM Controller section.)

The address ranges of the two memory banks (RAS0n and RAS1n) are continuous around the midpoint of the

DRAM memory bank. The RASn[1] starting address is 03000000h and grows larger based on the size of the

memory. The end of the RASn[0] bank ends at 03000000h and grows smaller from that point. Each bank has

separate configuration controls. The memory range is programmed through the address multiplexer selections for

bank 0 and bank 1 in the DRAMCtrl register.

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