MFC2000 datasheet(25/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

3-5

Table 3-1. Pin Description (5 of 6)

Pin Name

Pin No.

I/O

Input

Type

Output

Type

Pin Description

SDADDR[12:0]

V20,W20,Y20,

W19,Y19,W18,

Y18,W17,Y17,V

16,W16,Y16,V1

2XT3V

Countach (S)DRAM address bus (13 pins)

SDCASn

U20

2XT3V

Countach (S)DRAM column address strobe (active

low)

SDRASn

V19

2XT3V

Countach (S)DRAM row address strobe (active

low)

SDWRn

V18

2XT3V

Countach (S)DRAM write strobe (active low)

SDCSn

V17

2XT3V

Countach (S)DRAM chip select

SDCLK100MHz

M19

5VT

2XT5VT

Countach (S)DRAM clock

USB_Dp

I/O

Positive data input/output pin for USB

USB_Dn

I/O

Negative data input/output pin for USB

SDAA_PWRCLK

I/O

Positive power/clock output from SSD

SDAA_PWRCLKn

I/O

Negative power/clock output from SSD

SDAA_DIBp

I/O

Positive data input/output pin for SDAA

SDAA_DIBn

I/O

Negative data input/output pin for SDAA

EV_VD[0]/EADC_D[4]/ MREQn

W12

I/O

2XT3V

External video data [0] input for VIP or external

ADC data [4] input or Memory Request (active

low)-indicates that the following cycle is a memory

access.

EV_VD[1]/EADC_D[5]

U12

I/O

2XT3V

External video data [1] input for VIP or external

ADC data [5] input

EV_VD[2]/EADC_D[6]/ OPCn

Y13

I/O

2XT3V

External video data [2] input for VIP or external

ADC data [6] input or Op Code fetch (active low)-

LOW indicates that the processor is fetching an

instruction from memory.

EV_VD[3]/EADC_D[7]

W13

I/O

2XT3V

External video data [3] input for VIP or external

ADC data [7] input

EV_VD[4]/EADC_D[8]/ MAS[0]

U13

I/O

2XT3V

External video data [4] input for VIP or external

ADC data [8] input or Memory access size

MAS[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 -

Reserved during the normal operation

EV_VD[5]/EADC_D[9]/ MAS[1]

Y14

I/O

2XT3V

External video data [5] input for VIP or external

ADC data [9] input or Memory access size

MAS[1:0]: 00 - byte, 01 - halfword, 10 - word, 11 -

Reserved during the normal operation

EV_VD[6]/EADC_D[10]

W14

I/O

2XT3V

External video data [6] input for VIP or external

ADC data [10] input

EV_VD[7]/EADC_D11]/

ABORT

V14

I/O

2XT3V

External video data [7] input for VIP or external

ADC data [11] input or aborted bus cycle-the

address selected is outside of CS’s address

ranges.

EV_CLK

V13

H3V

(Hysteresis) External video clock input

W_Rn

N19

D5VT

2XT5VT

(Pull down) The bus access is a read operation

when W_Rn is LOW and write when W_Rn is

HIGH.

XAKn

N18

U5VT

2XT5VT

(Pull up) SIU Transaction Acknowledge. The

D[15:0] data will be transferred during this MCLK

cycle.

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