MFC2000 datasheet(56/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-26

Conexant

100723A

The MFC2000 assigns 4 multi-function pins (AE[2], AO[2], AE[3], and AO[3]) to facilitate the interleave access.

SIU generates 4 signals on these 4 pins to control ROMs for the following types of interleave accesses.

•

In 2-way interleave mode, MFC2000 pins AE[2] ,AO[2], AE[3], and AO[3] are connected to pin A[1:0] of the

even and odd external ROMs. MFC2000 pins A[1:0] are used to enable the ROM’s data busses.

ROMCSn

A23

EVEN

A23

ODD

A[25]

A[4]

AE[3]

AO[3]

AE[2]

AO[2]

Q-SW

A[1]

A[0]

RDn

Figure 4-4. 2-Way Interleave ROM Connection

•

The ROMCSn can be programmed to have up to 7 wait states for the initial access, and up to 1 wait state for

the sub-sequential access.

•

The write access to the ROM chip select area (ROMCSn) is allowed. It is customer’s choice to use it or not.

•

To use NOR-type flash memory in the ROM chip select area, WREn and WROn are designed to be used as

the write strobes for the different banks in the interleave mode (not for the higher and lower bytes). Therefore,

the 16-bit wide flash memory should be used in order to avoid the extra glue logic.

•

For non-interleave mode flash memory in the ROM chip select area, the WROn is used to access the higher

byte of the 16-bit data bus and the WREn is used to access the lower byte of the 16-bit data bus.

Assume that W wait states are needed for the initial access to ROM and S wait states (S = 0 or 1) for the sub-

sequential access according to the CPU clock frequency and the ROM speed. For a burst of 8 half-words

interleave access, the wait state of each half-word access, assuming the starting address’s A[3:1]=000. We can

have the following table show all different access modes for reading from ROM.

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