MFC2000 datasheet(93/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-63

Note:

Power_down1 and power_down2 are output signals from the power-down detection

circuit 1 and 2.

Bit12:

Betrstn Detected

This bit indicates that a betrstn occurred. To clear this bit, a 1 must be

written to this bit.

Bit11:

This bit indicates that a power down occurred, but no lockout was set

within the 1-2 second period. The lockout timer initiated the lockenn to

create the lockout condition. Once the lockout condition occurs, if the

power down signal is high, the chip will come out of reset after a pud1

delay. To clear this bit a 1 must be written to this bit.

Bit10:

SRAM Chip Select Enable

This bit enables the SRAM chip select CSN0.

Bit 9:

Bank 1 Interface Size

This register defines whether the data bus to the bank 1 DRAMs is 8

bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[1]

and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses

RASn[1] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface

uses RASn[1], CASEn[1:0], and CASOn[1:0].

Bit 8:

Bank 0 Interface Size

This register defines whether the data bus to the bank 0 DRAMs is 8

bits wide or 16 bits wide. An 8-bit wide DRAM interface uses RASn[0]

and CASOn[0]. A 16-bit wide non-interleaved DRAM interface uses

RASn[0] and CASOn[1:0]. A 16-bit wide interleaved DRAM interface

uses RASn[0], CASEn[1:0], and CASOn[1:0].

Bits 7-6:

DRAM Battery Backup Time

These bits control the amount of time that the DRAM controller will

spend refreshing the DRAMs when in the battery backup mode. After

reset when the CPU is being released to run, the CPU will not be able

to write data to bits 7 and 6 of the BackupConfig register immediately

since the immediate write will not take effect. The CPU must wait at

least one oscillator clock cycle before writing data into bits 7 and 6.

Bit 7

Bit 6

Battery Backup Duration:

No battery backup (default)

1-2 days

2-3 days

Infinite

Bit 5-4:

DRAM Refresh Rate

These bits are used to set up the DRAM refresh rate. See the following table:

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