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MFC2000 Datasheet(PDF) 88 Page - List of Unclassifed Manufacturers

Part # MFC2000
Description  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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MFC2000 Datasheet(HTML) 88 Page - List of Unclassifed Manufacturers

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MFC2000 Multifunctional Peripheral Controller 2000
Hardware Description
4-58
Conexant
100723A
Table 4-14. DRAM Row/Column Configuration
Memory Size
Address Multiplex
Setting
Supported/Not Supported
Row/Column Configuration
8-bit
16-bit
2-wy
intrl.
Row
Column
256K x 8
000
000
000
Supported
9
9
256K x 16 DRAMs
000
000
000
Supported
9
9
---
---
---
Not Supported
10
8
512K x 8
000
000
000
Supported
10
9
1M x 8
001
001
001
Supported
10
10
1M x 16 DRAMs
001
001
001
Supported
10
10
---
---
---
Not Supported
12
8
4M x 8
010
010
100
Supported
11
11
4M x 16 DRAMs
001
111
101
Supported
12
10
---
---
---
Not Supported
13
9
16M x 8
011
110
---
Supported
12
12
---
---
---
Not Supported
13
11
4.5.1.4
Refresh Operation
DRAM Refresh is performed automatically using the CAS-before-RAS method. Three different refresh speeds are
supported: slow, normal and fast. These speeds are selected by bits in the backup configuration register. The
refresh time is based on the crystal oscillator frequency and the refresh rate that is selected. During prime power
when it is time to refresh the DRAM, a CAS-before-RAS refresh cycle will be inserted. If the DRAM is being
accessed when a DRAM refresh is requested, the refresh cycle is not inserted until the access is complete. The
maximum burst length that the DRAM Controller will see is 8 halfwords (i.e., the maximum burst length coincides
with the CACHE line size). The maximum burst length is controlled by the SIU with the DRAMBURST signal that
is sent to the DRAM Controller.



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