MFC2000 datasheet(102/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-72

Conexant

100723A

4.6

Flash Memory Controller

The Flash memory controller provides an interface for both NAND and NOR type flash memory devices. Up to

two NOR type Flash memory devices or two NAND type devices can be connected to the ASIC. FCS0n and

FCS1n pins are the flash memory control pins. FWRn and FRDn are the flash read and write signals for NAND

type devices. Additional pins are required to interface to NAND type flash memory devices. GPIO pins can be

used as NAND type flash memory control signals.

Figure 4-30 shows the structure of the flash controller. It consists of an address and chip select generator block

and a read/write control block. The address and chip select generator block provides up to 21 address lines and 2

chip select signals for the flash memory devices. The read/write control block provides read and write strobes for

NAND type devices.

4.6.1

Supported Flash Memory

The flash memory controller supports the following types of Flash memory and their equivalents:

Flash Memory

Size

Type

INTEL

28F400BL/28F004BL-150

512 kB

NOR type

28F400BX/28F004BX-80, -120

512 kB

NOR type

AMD

Am29F040-70, -90, -120, -150

512 kB

NOR type

Samsung

KM29N040/080-150

512 kB/1 MB

NAND type

Note:

This ASIC also supports 1MB and 2MB NOR-type flash memory if the specified timing

can be matched.

4.6.2

Functional Description

4.6.2.1

Interfacing Flash Memory

The two types of flash memory that are supported require separate interface control options. NOR type devices

are bus oriented and can be connected to the CPU bus. The ASIC provides address signals to access the

memory space and provides the chip select signals. NAND type devices are special purpose peripherals with a

specialized interface requiring no address bus signals. The ASIC will use dedicated pins and GPIO pins to

interface with the NAND flash control and status lines.

4.6.2.2

NOR Type Flash Memory

NOR type devices can be used for both firmware code memory and for data memory. Accesses are performed

using normal bus operations. Reading data is performed with a bus read. Programming bytes or erasing sectors

requires multiple bus cycles. The CPU writes the command sequences required by the flash memory; then it polls

the flash memory’s status until the operation is complete.

The data address space is available in two separate blocks; the first block of memory is from 00800000h to

009FFFFFh (2Mbyte block) and the other is from 00A00000h to 00BFFFFFh (2Mbyte block). When the CPU

accesses the address range 00800000h - 009FFFFFh, FCS0n is activated. When the CPU accesses the address

range 00A00000h - 00BFFFFFh, FCS1n is activated. When using FCS0n and FCS1n for NOR-type flash

memory, the NAND-type bit (bit 6) of the FlashCtrl register must be set to 0. The FlashCtrl register is described in

the SIU section of the Hardware Description.

The NOR type flash interface consists of:

•

FCSn[1:0]: The two flash device selection signals. To use FCSn[1:0], bit 6 of the FlashCtrl register must be

set to 0.

•

A[20:0]: The external address bus for 2MB address range.

•

RDn and WREn/WROn: The external bus read and write strobes.

•

D[15:0]: The external data bus.

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