MFC2000 datasheet(106/426 Pages) ETC

106 / 426 page

MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-76

Conexant

100723A

4.6.4

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

NANDFlash

(NANDFLSH)

00C00001h

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

NANDFlash

(NANDFLSH)

00C00000h

Reading this location activates the FRDn signal. Writing to this location activates the FWRn signal. No

physical register exists for this location.

Rst. Value

xxh

Read Value

00h

activates the FRDn signal. Writing to this register activates the FWRn signal. FCLE, FALE, and FRDY must be

setup through the GPIO pins and FCSn[1:0] must be setup through the FlashCtrl register prior to accessing the

NANDFlash register. FCLE, FALE, and FRDY must be cleared through the GPIO pins and FCSn[1:0] must be

cleared through the FlashCtrl register after the register access.

Data written to this register is output on the data bus. When reading this register the flash memory data is placed

on the internal CPU bus. The NANDFlash register is only an address location; no register actually exists.

4.7

DMA Controller

4.7.1

General Description

•

The AMFPC is equipped with thirteen physically arbitrated DMA Channels assigned to either internal or

external requests.

•

Each channel provides its own 26-bit address for data access

•

The DMA channel address registers are made up of two programmable half word read/write registers, making

up a 26-bit counter (64MB).

•

Minimum DMA acknowledge delay is 2 System Clocks.

•

Maximum DMA acknowledge delay depends on the number of pending higher priority DMA requests and the

length of associated bus cycles including wait states and halt states due to DMA/DRAM refresh cycle

collisions.

•

Channel Specific Unique Features

⇒ Double Buffered Address and Block Size

This channel is equipped with a double buffered DMA address counter and Block Size register. This

allows firmware to set up the DMA address and Block Size values for the next block access while the

current one is active. When the DMA channel reaches it’s Block Size limit it issues an interrupt, and if a

new value has been written into the buffers (Buffer Loaded Flag is set), this value is transferred to the

address counter and/or Block Size register. The interrupt is cleared upon writing to the Block Size Buffer

⇒ DMA Block Size

An Access Block Size Counter is available to limit the number of DMA access in a given block. Once this

counter is set, it will keep track of the number of DMA access. Once the limit has been reached a CPU

interrupt will be set and no further accesses will be allowed until the register is reset. The IRQDMA is

activated at the falling edge of DMAACK.

MFC2000 Datasheet(PDF) 106 Page - List of Unclassifed Manufacturers

MFC2000 Datasheet(HTML) 106 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL