MFC2000 datasheet(108/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-78

Conexant

100723A

Each of the DMA channels, its function, and its characteristics are provided in Table 4-17.

Table 4-17. DMA Channel Functions and Characteristics

DMA

Channel

Function

Characteristics

USB data to/from memory for

PC print, PC fax TX, PC Fax

RX, PC scan

DMA Block Size Limit with CPU Interrupt via PIO/USB Interrupt,

4 logical DMA Channels, DMA address and Block Size double buffered, each Read/Write

selectable, halfword DMA data access only.

External DMA access only.

Normal and delayed ACK, Read/Write selectable, byte and halfword DMA data access

selectable.

External DMA Request only

Bit Rotation Access

(Output)

Address Jump Control, DMA Block Size Limit with Interrupt to IRQ Controller, Burst Mode,

Double Buffered Control Registers

Read/Write, External Request (Generates a DisDrive to disable the Bus IF output drivers to

for external memory writes.) External Request to the DMA controller may be delayed from

1 to 2 clocks for synchronization.

Bit Rotation Access (Input)

Address Jump Control (Controlled by Bit Rotation Block see table4.8.2-1)

Read Only, Internal Request. (MAS is always set to ½ word)

Countach to ARM Memory

(c2a)

Data write only, halfword DMA data access only

ARM Memory to Countach

(a2c)

Data read only, DMA Block Size Limit (16 kB), Interrupt to IRQ Controller

halfword DMA data access only.

Read/Write T4 Uncoded data

from/to Line Buffer to/from T4

Logic

Throttle Control

Read/Write, Internal Request

(MAS is always set to ½ word)

Read T.4 Reference Line from

the Line Buffer to T.4 logic

Read Only, Internal Request

(MAS is always set to ½ word)

T4 Resolution Converted data,

Line Buffer Access

Disable Address Count for read modify write

Read/Write, Internal Request, Read Modify Write Control

(MAS is always set to ½ word)

Bi-level resolution conversion

logic

DMA Block Size Limit. Interrupt to IRQ Controller

(MAS is always set to ½ word)

Read/Write T4 Coded data

from/to Page Memory to/from

T4 Logic

Throttle control

Address Block Size Limit, Interrupt to IRQ Controller

Read/Write, Internal Request

(MAS is always set to ½ word)

P1284 to Memory

DMA Block Size Limit with CPU Interrupt via PIO Interrupt,

Read/Write (Control Bit), Internal Request

Memory to P1284

DMA Block Size Limit with CPU Interrupt via PIO Interrupt,

Read/Write (Control Bit), Internal Request

(MAS is always set to ½ word)

Notes:

DMA Channel 0 has the highest priority.

"AD" means address.

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