MFC2000 datasheet(110/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-80

Conexant

100723A

cycle DMA read the requesting device must capture the data on the falling edge of the peripheral DMA

acknowledge.

If a sequential DMA access burst is desired, the peripheral must also activate the sequential access indicator at

the time of the initial request and must be cleared at the end of the next to the last DMA cycle. The DMA request

must be deactivated during the final DMA cycle, on the 1

st rising edge of the SIUCLK. The peripheral must also

capture (read), or drive the next datum onto the data bus on each rising edge of the SIUCLK when the DMA

acknowledge is active. During sequential burst accesses the Read/Write control and DMA address count controls

must remain static.

4.7.3.2

External DMA requests

The external device activates the DMA request signal (DMAREQ) at any time when it wants to do the single DMA

access operation. The MFC2000 chip double synchronizes the DMAREQ signal internally to avoid the meta-

stable case. After external DMA request has been issued, the associated acknowledge signal is activated with a

minimum delay of 5 internal SIUCLK cycles. The external device must deactivate DMAREQ after the associated

acknowledge signal is activated and before the end of this DMA cycle. If the DMA request continues to be

activated by the external DMA requesting device, the external DMA requesting device will get the second

DMAACK signal for the next single data transfer, when system bus is ready.

The MFC2000 chip continues to perform single DMA access as long as the DMAREQ is kept active by the

external DMA requesting device.

DMAACK is used similarly as chip select to indicate the DMA access cycle is ready for the external DMA

requesting device. The delay path within the MFC2000 is longer for DMAACK than for RDn; however, the actual

amount of skew between the two signals is dependent on their relative loading at the system board level. If RDn

has excessive delay, the DMAACK can be programmed to extend it an extra half SIUCLK cycle.

SIUCLK

Ext. DMAACK

DMA address

Ext. address bus

DMA data

Ext. data bus

Ext. DMAREQ

tDRS

tAD

tDADN

tDIH

tRD

tDADF

RDn

DMA Cycle

tRD

Figure 4-32: External DMA Read Timing (Single Access, One Wait State)

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