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MFC2000 Datasheet(PDF) 111 Page - List of Unclassifed Manufacturers

Part # MFC2000
Description  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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MFC2000 Datasheet(HTML) 111 Page - List of Unclassifed Manufacturers

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Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
100723A
Conexant
4-81
SIUCLK
Ext. DMAACK
DMA address
Ext. address bus
DMA data
Ext. data bus
Ext. DMAREQ
tDRS
tAD
tDADN
tDOH
tWD
tDADF
WREn
DMA Cycle
tWD
Figure 4-33. External DMA Write Timing (Single Access, One Wait State)
Parameter
Symbol
Min
Max
Units
RDn delay (ext. load = 50pF)
tRD
25
ns
WRn delay (ext. load = 50pF)
tWD
25
ns
Address delay (ext. load = 50pF)
tAD
24
ns
DMAACK on delay time (ext. load = 15pF)
tDADN
10
ns
DMAACK off delay time (ext. load = 15pF)
tDADF
5ns
DMA Input Data Hold
tDIH
8
ns
DMA Output Data Hold (ext. load = 50pF)
tDOH
8
25
ns
RASn delay (ext. load = 40pF)
tRASD
25
ns
CASn delay (ext. load = 40pF)
tCASD
20
ns
DWRn delay (ext. load = 40pF)
tDWD
-20
ns
Notes:
1.
SIUCLK is the internal system interface clock. These values is for SIUCLK = 30 MHz.
2.
The external DMA request set-up time (tDRS) is not required because this input is double
synchronized internally for the meta-stable case.



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