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MFC2000 Datasheet(PDF) 115 Page - List of Unclassifed Manufacturers

Part # MFC2000
Description  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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MFC2000 Datasheet(HTML) 115 Page - List of Unclassifed Manufacturers

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Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
100723A
Conexant
4-85
Address:ch0cscntl
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
DMA 0 Configuration
(DMA0config)
$xx81B1
Channel
Enable
LC3
Channel
Enable
LC2
Channel
Enable
LC1
Channel
Enable
LC0
Read/Write
Mode
LC3
Read/Write
Mode
LC2
Read/Write
Mode
LC1
Read/Write
Mode
LC0
Rst. Value
00h
Read
Value 00h
Address:ch0cscntl
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
DMA 0 Configuration
(DMA0config)
$xx81B0
Not Used
Not Used
IRQ
LC3
IRQ
LC3
IRQ
LC3
IRQ
LC3
Not Used
DMA0
Enable
Rst. Value
00h
Read
Value 00h
Bit 15-12: Logical Channel Enable
Setting the bit to 1 will allow operation of the logical channel, setting
the bit to 0 will disable the channel and clear it’s registers.
Bit 11-8:
Read/Write Mode Select.
Selects the data direction. Read = 1, Write = 0
Bit 5-2:
Interrupts from the individual Logical Channels. Clear by writing to the
block size register.
Bit 0:
Setting this bit to 1 will enable DMA Channel 0. Setting this bit to 0 will
fore all of the logical channels into their reset state.
Address:
chcsl[10:0]
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
DMAUSB Low
Counter
(DMAiCntlo)
DMA0-10
Addr.
Bit 15
DMA0-10
Addr.
Bit 14
DMA0-10
Addr.
Bit 13
DMA0-10
Addr.
Bit 12
DMA0-10
Addr.
Bit 11
DMA0-10
Addr.
Bit 10
DMA0-10
Addr.
Bit 9
DMA0-10
Addr.
Bit 8
Rst. Value
00h
Read
Value 00h
Address:
chcsl[10:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
DMAUSB Low
Counter
(DMAiCntlo)
DMA0-10
Addr.
Bit 7
DMA0-10
Addr.
Bit 6
DMA0-10
Addr.
Bit 5
DMA0-10
Addr.
Bit 4
DMA0-10
Addr.
Bit 3
DMA0-10
Addr.
Bit 2
DMA0-10
Addr.
Bit 1
DMA0-10
Addr.
Bit 0
Rst. Value
00h
Read
Value 00h
•
DMAUSB Channel 0-3 Lower Address Counter Value. Address will only count by 2.
•
Reading this register will return the active Address value when the last USBACK occurred.
Note: This register is double buffered. Writing to this location twice will load the active register as
well as the buffer register. Upon a block limit interrupt, the buffer value will be activated therefor
a new buffered value should be written to this register.
DMAUSB0CntLo
01FF81C8-C9
DMAUSB1CntLo
01FF81CE-CF
DMAUSB2CntLo
01FF81D4-D5
DMAUSB3CntLo
01FF81DA-DB



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