MFC2000 datasheet(117/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-87

Address:ch4csbs

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

DMAUSB Transfer

Block Size Reg.

(DMAUSBBlockSize

)

USB Channel

Enable = 1

Stop At

Block

Upper six bits of the Block Size Counter

Rst.

Value

00h

Read

Value 00h

Address:ch4csbs

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

DMAUSBTransfer

Block Size Reg.

(DMAUSBBlockSize

)

Low Byte Value for USB Memory Block Size Counter

Rst. Value

00h

Read

Value 00h

Block Size data written to this register will be placed into the inactive Block Size register. This register will become

active once the prior block has completed (USB IRQ). Reading this register will return the Block Size value when

the last USBACK occurred. Writing to this will initialize the logical channel. Therefore, when setting up a logical

channel, this register should be written to last.

Note:

This register is double buffered. Writing to this location twice will load the active register

as well as the buffer register. Upon a block limit interrupt, the buffer value will be activated

therefor a new buffered value should be written to this register.

•

DMA USB Channel Block Size Limit Counter

DMAUSB0 BlkSiz

01FF81CC-CD

DMAUSB1 BlkSiz

01FF81D2-D3

DMAUSB2 BlkSiz

01FF81D8-D9

DMAUSB3 BlkSiz

01FF81DE-DF

Bits [13:0] DMAUSB Memory Block Size

The block size of DMA channel can range from 1 – 16383 DMA

transfers.

The Block Size counter will decrement regardless of the DMA Address

counter’s activity. The block size register content is 0000h when the

block size limit is reached.

When the block size reaches its limit, an IRQ will be generated upon

the next Channel ACK. Writing To this register will clear the IRQ.

Bit 14 Note:

When this bit is set, the DMA channel will disable it’s self until a new block size

is entered.

If this bit is 0, when a block limit is reached the next block size will be downloaded into the

counter along with the next DMA address and transfers will continue within the new block. Upon

the next channel ACK, an IRQ will be generated.

Bit 15:

This bit must be set at all times to enable the channel and is not part

of the double buffering process.

MFC2000 Datasheet(PDF) 117 Page - List of Unclassifed Manufacturers

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