 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MFC2000 Datasheet(PDF) 120 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
MFC2000 Datasheet(HTML) 120 Page - List of Unclassifed Manufacturers |
|
|
120 / 426 page  MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 4-90 Conexant 100723A Address:ch2csbbs Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: DMA Ch2 Buffered Transfer Block Size Reg. (DMA2BfBlockSize) $xx81B7 Ch2 Enable = 1 Not Used Not Used Not Used Not Used Not Used Upper two bits of the Block Size counter Rst. Value 00h Read Value 00h Address:ch2csbbs Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: DMA Ch2 Buffered Transfer Block Size Low Byte Reg. (DMA2BfBlockSizeLo) $xx81B6 Low Byte Value for the External DMA Block Size Counter Rst. Value 00h Read Value 00h • DMA Channel 2 Buffered Block Size Limit Counter • block size of DMA channel 2 (1/2 Words) − Unlimited block size (block size = ∞ ): bit[7:0] of the DMA2BlockSize register = 00h bit[9:8] of the DMA2BlockSize register = 00b. − Limited block size (block size = 1 - 1023) • The first transfer block size and the starting address must be set up in the DMA2BlkSize and DMA2 address registers. The second transfer block size and the starting address must be set up in the DMA2BufBlkSize and DMA2 buffered address registers. Then, Firmware only needs to update the DMA2BufBlkSize and DMA2 buffered address registers when the DMA channel 2 interrupt occurs. This allows preloading of the next block size and starting address before the DMA operation for the current block has completed. • The Buffered Block Size will be down loaded into the Block Size Counter when the current Block Size is reached and a new value has been written into this buffered block size register. Writing to this register will also clear the DMA channel 2 interrupt. • The block size can be written into the DMA2BufBlkSize register only when the value of bit 15 in the DMA2BlkSize register is set to 0. Address: chcsbl[2] Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: DMA Ch2 Buffered Low Counter (DMA2Cntblo) $xx818D DMAB2 Addr. Bit 15 DMAB2 Addr. Bit 14 DMAB2 Addr. Bit 13 DMAB2 Addr. Bit 12 DMAB2 Addr. Bit 11 DMAB2 Addr. Bit 10 DMAB2 Addr. Bit 9 DMAB2 Addr. Bit 8 Rst. Value 00h Read Value 00h Address: chcsbl[2] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: DMA Ch2 Buffered Low Counter (DMA2Cntblo) $xx818C DMAB2 Addr. Bit 7 DMAB2 Addr. Bit 6 DMAB2 Addr. Bit 5 DMAB2 Addr. Bit 4 DMAB2 Addr. Bit 3 DMAB2 Addr. Bit 2 DMAB2 Addr. Bit 1 DMAB2 Addr. Bit 0 Rst. Value 00h Read Value 00h • DMA Channel 2 Lower Buffered Address Counter Value • The Buffered Address Counter Value will be down loaded into the Address Counter when the current Block Size is reached and a new value has been written into this register. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
