MFC2000 datasheet(119/426 Pages) ETC

119 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-89

Bit 8:

If the Bit Rotation Block is selected (bit 6 = 0), and the external data

bus for the Print ASIC is byte wide, this bit needs to be ‘0’. If the Bit

Rotation Block is selected (bit 6 = 0), and the external data bus for the

Print ASIC is halfword wide, this bit needs to be ‘1’. If external memory

is selected (bit 6 = 1), the external bus data width for the Print ASIC

and external memory need to be matched (this bit is not used).

Bit 7:

Control bit definition is with reference to the DMA requested device

and controls the read/write signals during the DMA cycle. If it is set to

write, the write strobe will be active during the DMA cycle.

Bit 6:

If the Bit Rotation Block is selected ( bit 6 = 0), the DMA Request will

be held off when the Bit Rotation Block output register is not ready.

The ASIC output bus drivers will be disabled during external DMA

request write (bit 6 = 1 and bit 7 = 0).

Bit 5:

Controls the address count direction performed after each DMA cycle.

Bit 4-0:

These bits control how the address registers will count after each DMA

cycle. Note: If byte mode is set, the Count By 1 should be set.

Note: Requests to this channel are delayed by two clocks for synchronization.

Address:ch2csbs

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

DMA 2 Transfer

Block Size Reg.

(DMA2BlockSize)

$xx81B5

Channel 2

Enable = 1

Not Used

Upper two bits of the Block

Size counter

Rst. Value

00h

Read

Value 00h

Address:ch2csbs

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

DMA2 Transfer

Block Size Low

Byte Reg.

(DMA2BlockSizeLo)

$xx81B4

Low Byte Value for the External DMA Block Size Counter

Rst. Value

00h

Read

Value 00h

•

DMA Channel 2 Block Size Limit Counter

•

block size of DMA channel 2 (halfwords)

− Unlimited block size (block size =

∞ ):

bit[7:0] of the DMA2BlockSize register = 00h

bit[9:8] of the DMA2BlockSize register = 00b.

− Limited block size (block size = 1 - 1023)

•

The Block Size counter will decrement regardless of the DMA Address counter’s activity. The block size

•

Please see the operation description of DMA2BlkSize and DMA2BufBlkSize registers below (in the

MFC2000 Datasheet(PDF) 119 Page - List of Unclassifed Manufacturers

MFC2000 Datasheet(HTML) 119 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL