MFC2000 datasheet(107/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-77

⇒ Addressing Modes

All of the DMA Channels increment by 2 after each access. The external channels 1 and 2, can be set to

increment by 1 for byte wide peripherals. The count enable register allows the user to select which

address will increment after each access. However, Channels 2 and 3 have the additional functionality

allowing them to Increment or Decrement by a specified amount. Channel 2 is controlled by the values in

it’s control register. Channel 3 is controlled by control signals generated in the Bit Rotation Logic.

⇒ Priority

Shows the overall channel priority in the DMA request arbitrator, with 1 as the highest.

⇒ Uninterrupted Burst mode

Allows the requesting device to hold the Burst DMA Request active (PSEQ), to transfer multiple bytes of

uninterrupted data. If higher priority requests occur during the burst operation they will be ignored.

This operation is mainly for high speed DRAM access. Also during this mode, the read/write control and

the count controls must remain static.

⇒ Throttle Control

A Throttle Value can be set to allow 1 DMA access per a given time period. The throttle time period is a

product of the value set and the system clock.

⇒ Logical Channels

This single physical DMA channel is equipped with multiple logical channels that operate independent of

each other. Only one logical can be active at any time.

4.7.1

DMA Mode Summary

Table 4-16. Feature Matrix

Features

Channel

Double

Buffered

Control

Block Size

Limit

Address

Increment

Address

Decrement

Address

Jump

Priority

U-I

Burst

Mode

Other

Features

√√

√

Logical

√

√√

√

Byte

√√

√

√√

√

√√

√

√√

√

Throttle

√√

√

√√

√

√√

√

√√

√

Throttle

√√

√

√√

√

Throttle

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