MFC2000 datasheet(274/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

14-8

Conexant

100723A

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

T4 FIFO Bits

Remaining Register

(T4FIFOBitRem)

$01FF817B

(Not Used)

Rst. Value

xxh

Read Value:

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

T4 FIFO Bits

Remaining Register

(T4FIFOBitRem)

$01FF817A

(Not Used)

Bits remaining

Rst. Value

xxxx0000b

Read Value

x0000000b

Bit 15-4:

Not used

Bit 3-0:

Number of bits remaining in FIFO (holding register), with values

ranging from 0 to 15. The interpretation of bits remaining depends on

the direction of data flow. If the compressor/decompressor is emptying

the FIFO, bit remaining is the number of that contain data that have

yet to be processed. If the compressor/decompressor is filling the

FIFO, bits remaining is the number of bits that are empty.

T.4 data FIFO halfword[3:0] for the coded data to/from the external memory (for DMA channel 10):

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

T.4 Data FIFO

(T4Data1FIFOx)

data

bit 15

data

bit 14

data

bit 13

data

bit 12

data

bit 11

data

bit 10

data

bit 9

data

bit 8

Rst Value

xxh

Read

Value xxh

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

T.4 Data FIFO

(T4Data1FIFOx)

data

bit 7

data

bit 6

data

bit 5

data

bit 4

data

bit 3

data

bit 2

data

bit 1

data

bit 0

Rst Value

xxh

Read

Value xxh

•

Address assignment for T.4 Data FIFO halfword[3:0]

FIFO halfword

The register name

Address

FIFO halfword 3

T4DataFIFO3

01FF8117-16

FIFO halfword 2

T4DataFIFO2

01FF8115-14

FIFO halfword 1

T4DataFIFO1

01FF8113-12

FIFO halfword 0

T4DataFIFO0

01FF8111-10

MFC2000 Datasheet(PDF) 274 Page - List of Unclassifed Manufacturers

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