MFC2000 datasheet(344/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

17-22

Conexant

100723A

17.6 Firmware Operation

All the Parallel Port negotiations will be done in firmware.

17.6.1 Disabling All Hardware Handshaking

When hardware handshaking is disabled(MODE=0), software is then responsible for controlling the parallel port

interface. Software can control all parallel port operations including negotiation and termination phases, as well as

reverse channel transfers. This provides flexibility to adapt to existing protocols as they are revised and to new

protocols as they are created.

Software can control the BUSY and ACKn interface pins with the FBSY (force BUSY) and FACK (force ACKn)

bits in the Parallel Port Interface Register. The FBSY bit is OR’ed with the BUSY output from the PPI state

machine before driving the BUSY interface pin, and the FACK bit is NOR’ed with the ACKn output from the PPI

state machine before driving the ACKn interface pin. Normally the PPI state machine should be idle when using

FBSY and FACK. Even with all hardware handshaking disabled, the Parallel port register continues to latch

parallel port data on the leading edge of the STROBEn. Software can issue a RST in the Parallel Port Control

17.6.2 Software Interrupts

The following is a list of P1284 signal transition interrupts provided for ease of use:

SLCTINn

Rising and Falling

STROBEn

Rising and Falling (remains high until data is fetched from PPI)

INITn

Rising and Falling

AUTOFDn

Rising and Falling

DRX

Data Received

CRX

Command Received

IVT

Invalid Transition

RDX

Reverse Data Transmitted

HTE

Host Time-out Error

17.6.3 Interrupt Operation

There will be a bit corresponding to each interrupt in the interrupt enable register that enables the interrupt. When

the event corresponding to an interrupt occurs, this bit needs to be set at the following rising edge of the SIU

clock. The PPI Interface possesses 15 sources of interrupts. Each source can post an event in the interrupt status

interrupts have been in Section 17. The first eight interrupt events signal level changes that occur at the host

control signal input pins. Note that these events are detected after the host inputs are synchronized, digitally

filtered, and recorded in the parallel Port Interface Register.

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