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MFC2000 Datasheet(PDF) 363 Page - List of Unclassifed Manufacturers

Part # MFC2000
Description  Multifunctional Peripheral Controller 2000
PDF  426 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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MFC2000 Datasheet(HTML) 363 Page - List of Unclassifed Manufacturers

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Hardware Description
MFC 2000 Multifunctional Peripheral Controller 2000
100723A
Conexant
20-5
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
BellPhase
01FF80B9
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used) Rst. Value
xxh
Read Value
00h
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
BellPhase
01FF80B8 (R )
(Not Used)
(Not Used)
(Not Used)
(Not Used)
Bell Phase
Rst. Value
xxxx0000b
Read Value
00h
Register Description: Bell Phase Register
Bit 15-4:
Not Used
Bit 3-0:
Read only register returns current phase of the bell signal.
Address:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default:
BellCtrl
01FF80B5
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
(Not Used)
Rst. Value
xxh
Read Value
00h
Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default:
BellCtrl
01FF80B4
(Not Used)
(Not Used)
(Not Used)
(Not Used)
ModToneEn
b
1 = Enabled
RingerEnb
1=Ring
Mode
0=Bell Mode
BellDrvEnb
1 = Enabled
0 = Allow
Hi Z out
BellEnb
1 = Enabled
Rst. Value
xxxx0000b
Read Value
00h
Register Description: Bell Control Register
Bit 15-4:
Not Used
Bit 3:
Enables the ALTTone output to external pin but has no effect on the
Ringer Mode. If this signal is set to 0 the ALTTone output will be at 0.
Bit 2:
Sets the generator into Bell Mode or Ringer Mode (Ringer Mode
overrides bit 1 and does not allow the tristate condition.)
Bit 1:
In Bell Mode, it Controls weighter the output pin is always driven or
tristated during bell
phases 0, F, 8, and 7.
Bit 0:
Enables the Bell/Ringer counters to run. When this bit is set to 0, the
counters are held at the start of phase “F”.
Note:
After reset the Bell/Ringer pin will be tristated with the counters held at bell phase “0”.



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