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AD7293 Datasheet(PDF) 35 Page - Analog Devices

Part # AD7293
Description  12-Bit Power Amplifier Current Controller
PDF  78 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7293 Datasheet(HTML) 35 Page - Analog Devices

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Data Sheet
AD7293
Rev. B | Page 35 of 78
RESULT 1 (PAGE 0x01)
Table 29. Result 1 (Page 0x01)
Address
(Hex)
Name
Byte1
Access
Type1
Default
Value1
0x00
No op
N/A
N/A
0x00
0x01
Page select pointer
1
R/W
0x00
0x02
Conversion command2
1
W
N/A
0x03
Result
2
R
0x0000
0x04
DAC enable
1
R/W
0x00
0x05
GPIO
1
R/W
0x00
0x0C
Device ID
2
R
0x0018
0x0F
Software reset
2
R/W
0x0000
0x10
AVDD
2
R
0x0000
0x11
DACVDD-UNI
2
R
0x0000
0x12
DACVDD-BI
2
R
0x0000
0x13
AVSS
2
R
0x0000
0x14
BI-VOUT0MON
2
R
0x0000
0x15
BI-VOUT1MON
2
R
0x0000
0x16
BI-VOUT2MON
2
R
0x0000
0x17
BI-VOUT3MON
2
R
0x0000
0x28
RS0+MON
2
R
0x0000
0x29
RS1+MON
2
R
0x0000
0x2A
RS2+MON
2
R
0x0000
0x2B
RS3+MON
2
R
0x0000
1
N/A means not applicable.
2
Not a physical register.
Voltage Supply Monitor Result Registers (Register 0x10
to Register 0x13)
The ADC is used in its single-ended mode. The LSB size varies
with the different supply monitoring registers. AVDD and
DACVDD-BI are divided by 5, and DACVDD-UNI is divided by 20 to
scale within the 0 V to REFADC range. AVSS is level shifted to
within a −7.5 V to +2.5 V range, where 0x0000 equates to
approximately −7.5 V and 0xFFFF equates to approximately
+2.5 V. REFADC = 1.25 V.
Bipolar DAC Internal Monitor Result (BI-VOUT0MON to
BI-VOUT3MON) Registers (Register 0x14 to Register 0x17)
These registers store the 12-bit ADC results from the four
internal inputs for monitoring the bipolar DAC outputs in
open-loop mode or the integrator outputs in closed-loop mode.
The DAC monitoring channel voltages between −5 V and +5 V
are level shifted to the 0 V to REFADC range before conversions.
RSx+MON Result Registers (Register 0x28 to
Register 0x2B)
The voltages on the RSx+ pins (RSx+MON) are divided by 50 to
scale them to the 0 V to REFADC range. Use the ADC in single-
ended mode. The RSx+MON monitor result registers store the 12-
bit ADC results for the current sense supply channels.
Table 30. Monitor Register Configuration
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
[D3:D0]
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Reserved



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